1. Field
Exemplary embodiments of the present invention relate to a buffer control circuit, and more particularly, to a technology for controlling a buffer to accurately recognize the logic level of an input signal.
2. Description of the Related Art
As the data transmission speeds of various integrated circuits rapidly increase, high speed and high quality buffers are useful. In particular a buffer capable of correctly receiving a signal distorted due to inter-symbol interference or crosstalk is being developed.
FIG. 1 is a configuration diagram of a conventional buffer circuit.
Referring to FIG. 1, the buffer circuit includes a current supply unit 110, an amplifier type buffer 120 and an inverter type buffer 130.
The current supply unit 110 supplies current to be used by the amplifier type buffer 120. The current supply unit 110 may be configured by a current source well-known in the art.
The amplifier type buffer 120 is configured as a differential amplifier. The amplifier type buffer 120 compares an input signal VIN and a reference potential VREF and drives an output terminal V1 according to a comparison result. If the level of the input signal VIN is higher than the reference potential VREF, the output terminal V1 is driven to a high level, and if the level of the input signal VIN is lower than the reference potential VREF, the output terminal V1 is driven to a low level.
The inverter type buffer 130 receives and outputs a signal from the output terminal V1 of the amplifier type buffer 120. The inverter type buffer 130 is a buffer constituted by a logic gate, such as an inverter, a NAND gate, a NOR gate, and the like, which is placed at a rear end of the amplifier type buffer 120 in the buffer circuit. It is illustrated in the drawing that the inverter type buffer 130 includes two inverters.
FIGS. 2 and 3 are graphs showing the voltage levels of an output terminal V1 and an output terminal V2 in an ideal case and in a non-ideal case.
Referring to FIG. 2, the crossing point of the signal of the output terminal V1 and the signal of an output terminal V2 is the same as a reference potential VREF. In this case, when the input signal VIN is the same as the reference potential VREF, since the signal of the output terminal V1 and the signal of the output terminal V2 are at the reference potential VREF, the logic value of the input signal VIN may be accurately recognized.
Referring to FIG. 3, the crossing point of the signal of the output terminal V1 and the signal of the output terminal V2 is not the reference potential VREF. This is caused due to the fact that the logic threshold of the inverter is different from the reference potential VREF. The degree of significance of this phenomenon may vary according to a PVT variation of an integrated chip including the buffer circuit. In the case where the crossing point of the signal of the output terminal V1 and the signal of the output terminal V2 is not the reference potential VREF as shown in FIG. 3, when the input signal VIN has a high level, the input signal VIN may be erroneously recognized as a low level inside a chip, and when the input signal VIN has a low level, the input signal VIN may be erroneously recognized as a high level. In particular, where the input signal VIN is a periodic wave such as a clock, the duty of the periodic wave may be distorted.